/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */

[0] Fix | Delete

/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */

[1] Fix | Delete

#ifndef _USR_IDXD_H_

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#define _USR_IDXD_H_

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#include <stdint.h>

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/* Driver command error status */

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enum idxd_scmd_stat {

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IDXD_SCMD_DEV_ENABLED = 0x80000010,

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IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,

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IDXD_SCMD_WQ_ENABLED = 0x80000021,

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IDXD_SCMD_DEV_DMA_ERR = 0x80020000,

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IDXD_SCMD_WQ_NO_GRP = 0x80030000,

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IDXD_SCMD_WQ_NO_NAME = 0x80040000,

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IDXD_SCMD_WQ_NO_SVM = 0x80050000,

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IDXD_SCMD_WQ_NO_THRESH = 0x80060000,

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IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,

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IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,

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IDXD_SCMD_PERCPU_ERR = 0x80090000,

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IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,

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IDXD_SCMD_CDEV_ERR = 0x800b0000,

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IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,

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IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,

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IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,

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IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,

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IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,

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IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,

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};

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#define IDXD_SCMD_SOFTERR_MASK 0x80000000

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#define IDXD_SCMD_SOFTERR_SHIFT 16

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/* Descriptor flags */

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#define IDXD_OP_FLAG_FENCE 0x0001

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#define IDXD_OP_FLAG_BOF 0x0002

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#define IDXD_OP_FLAG_CRAV 0x0004

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#define IDXD_OP_FLAG_RCR 0x0008

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#define IDXD_OP_FLAG_RCI 0x0010

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#define IDXD_OP_FLAG_CRSTS 0x0020

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#define IDXD_OP_FLAG_CR 0x0080

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#define IDXD_OP_FLAG_CC 0x0100

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#define IDXD_OP_FLAG_ADDR1_TCS 0x0200

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#define IDXD_OP_FLAG_ADDR2_TCS 0x0400

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#define IDXD_OP_FLAG_ADDR3_TCS 0x0800

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#define IDXD_OP_FLAG_CR_TCS 0x1000

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#define IDXD_OP_FLAG_STORD 0x2000

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#define IDXD_OP_FLAG_DRDBK 0x4000

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#define IDXD_OP_FLAG_DSTS 0x8000

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[49] Fix | Delete

/* IAX */

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#define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000

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#define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000

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#define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000

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#define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000

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#define IDXD_OP_FLAG_SRC2_STS 0x100000

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#define IDXD_OP_FLAG_CRC_RFC3720 0x200000

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[57] Fix | Delete

/* Opcode */

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enum dsa_opcode {

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DSA_OPCODE_NOOP = 0,

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DSA_OPCODE_BATCH,

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DSA_OPCODE_DRAIN,

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DSA_OPCODE_MEMMOVE,

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DSA_OPCODE_MEMFILL,

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DSA_OPCODE_COMPARE,

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DSA_OPCODE_COMPVAL,

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DSA_OPCODE_CR_DELTA,

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DSA_OPCODE_AP_DELTA,

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DSA_OPCODE_DUALCAST,

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DSA_OPCODE_CRCGEN = 0x10,

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DSA_OPCODE_COPY_CRC,

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DSA_OPCODE_DIF_CHECK,

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DSA_OPCODE_DIF_INS,

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DSA_OPCODE_DIF_STRP,

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DSA_OPCODE_DIF_UPDT,

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DSA_OPCODE_CFLUSH = 0x20,

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};

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enum iax_opcode {

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IAX_OPCODE_NOOP = 0,

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IAX_OPCODE_DRAIN = 2,

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IAX_OPCODE_MEMMOVE,

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IAX_OPCODE_DECOMPRESS = 0x42,

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IAX_OPCODE_COMPRESS,

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IAX_OPCODE_CRC64,

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IAX_OPCODE_ZERO_DECOMP_32 = 0x48,

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IAX_OPCODE_ZERO_DECOMP_16,

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IAX_OPCODE_ZERO_COMP_32 = 0x4c,

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IAX_OPCODE_ZERO_COMP_16,

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IAX_OPCODE_SCAN = 0x50,

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IAX_OPCODE_SET_MEMBER,

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IAX_OPCODE_EXTRACT,

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IAX_OPCODE_SELECT,

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IAX_OPCODE_RLE_BURST,

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IAX_OPCODE_FIND_UNIQUE,

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IAX_OPCODE_EXPAND,

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};

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[98] Fix | Delete

/* Completion record status */

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enum dsa_completion_status {

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DSA_COMP_NONE = 0,

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DSA_COMP_SUCCESS,

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DSA_COMP_SUCCESS_PRED,

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DSA_COMP_PAGE_FAULT_NOBOF,

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DSA_COMP_PAGE_FAULT_IR,

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DSA_COMP_BATCH_FAIL,

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DSA_COMP_BATCH_PAGE_FAULT,

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DSA_COMP_DR_OFFSET_NOINC,

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DSA_COMP_DR_OFFSET_ERANGE,

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DSA_COMP_DIF_ERR,

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DSA_COMP_BAD_OPCODE = 0x10,

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DSA_COMP_INVALID_FLAGS,

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DSA_COMP_NOZERO_RESERVE,

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DSA_COMP_XFER_ERANGE,

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DSA_COMP_DESC_CNT_ERANGE,

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DSA_COMP_DR_ERANGE,

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DSA_COMP_OVERLAP_BUFFERS,

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DSA_COMP_DCAST_ERR,

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DSA_COMP_DESCLIST_ALIGN,

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DSA_COMP_INT_HANDLE_INVAL,

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DSA_COMP_CRA_XLAT,

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DSA_COMP_CRA_ALIGN,

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DSA_COMP_ADDR_ALIGN,

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DSA_COMP_PRIV_BAD,

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DSA_COMP_TRAFFIC_CLASS_CONF,

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DSA_COMP_PFAULT_RDBA,

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DSA_COMP_HW_ERR1,

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DSA_COMP_HW_ERR_DRB,

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DSA_COMP_TRANSLATION_FAIL,

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};

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enum iax_completion_status {

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IAX_COMP_NONE = 0,

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IAX_COMP_SUCCESS,

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IAX_COMP_PAGE_FAULT_IR = 0x04,

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IAX_COMP_ANALYTICS_ERROR = 0x0a,

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IAX_COMP_OUTBUF_OVERFLOW,

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IAX_COMP_BAD_OPCODE = 0x10,

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IAX_COMP_INVALID_FLAGS,

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IAX_COMP_NOZERO_RESERVE,

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IAX_COMP_INVALID_SIZE,

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IAX_COMP_OVERLAP_BUFFERS = 0x16,

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IAX_COMP_INT_HANDLE_INVAL = 0x19,

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IAX_COMP_CRA_XLAT,

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IAX_COMP_CRA_ALIGN,

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IAX_COMP_ADDR_ALIGN,

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IAX_COMP_PRIV_BAD,

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IAX_COMP_TRAFFIC_CLASS_CONF,

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IAX_COMP_PFAULT_RDBA,

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IAX_COMP_HW_ERR1,

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IAX_COMP_HW_ERR_DRB,

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IAX_COMP_TRANSLATION_FAIL,

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IAX_COMP_PRS_TIMEOUT,

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IAX_COMP_WATCHDOG,

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IAX_COMP_INVALID_COMP_FLAG = 0x30,

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IAX_COMP_INVALID_FILTER_FLAG,

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IAX_COMP_INVALID_INPUT_SIZE,

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IAX_COMP_INVALID_NUM_ELEMS,

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IAX_COMP_INVALID_SRC1_WIDTH,

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IAX_COMP_INVALID_INVERT_OUT,

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};

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#define DSA_COMP_STATUS_MASK 0x7f

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#define DSA_COMP_STATUS_WRITE 0x80

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struct dsa_hw_desc {

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uint32_t pasid:20;

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uint32_t rsvd:11;

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uint32_t priv:1;

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uint32_t flags:24;

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uint32_t opcode:8;

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uint64_t completion_addr;

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union {

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uint64_t src_addr;

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uint64_t rdback_addr;

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uint64_t pattern;

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uint64_t desc_list_addr;

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};

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union {

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uint64_t dst_addr;

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uint64_t rdback_addr2;

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uint64_t src2_addr;

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uint64_t comp_pattern;

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};

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union {

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uint32_t xfer_size;

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uint32_t desc_count;

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};

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uint16_t int_handle;

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uint16_t rsvd1;

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union {

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uint8_t expected_res;

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/* create delta record */

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struct {

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uint64_t delta_addr;

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uint32_t max_delta_size;

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uint32_t delt_rsvd;

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uint8_t expected_res_mask;

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};

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uint32_t delta_rec_size;

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uint64_t dest2;

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/* CRC */

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struct {

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uint32_t crc_seed;

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uint32_t crc_rsvd;

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uint64_t seed_addr;

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};

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/* DIF check or strip */

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struct {

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uint8_t src_dif_flags;

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uint8_t dif_chk_res;

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uint8_t dif_chk_flags;

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uint8_t dif_chk_res2[5];

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uint32_t chk_ref_tag_seed;

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uint16_t chk_app_tag_mask;

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uint16_t chk_app_tag_seed;

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};

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/* DIF insert */

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struct {

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uint8_t dif_ins_res;

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uint8_t dest_dif_flag;

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uint8_t dif_ins_flags;

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uint8_t dif_ins_res2[13];

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uint32_t ins_ref_tag_seed;

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uint16_t ins_app_tag_mask;

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uint16_t ins_app_tag_seed;

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};

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/* DIF update */

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struct {

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uint8_t src_upd_flags;

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uint8_t upd_dest_flags;

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uint8_t dif_upd_flags;

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uint8_t dif_upd_res[5];

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uint32_t src_ref_tag_seed;

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uint16_t src_app_tag_mask;

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uint16_t src_app_tag_seed;

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uint32_t dest_ref_tag_seed;

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uint16_t dest_app_tag_mask;

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uint16_t dest_app_tag_seed;

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};

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[241] Fix | Delete

uint8_t op_specific[24];

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};

[243] Fix | Delete

} __attribute__((packed));

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struct iax_hw_desc {

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uint32_t pasid:20;

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uint32_t rsvd:11;

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uint32_t priv:1;

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uint32_t flags:24;

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uint32_t opcode:8;

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uint64_t completion_addr;

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uint64_t src1_addr;

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uint64_t dst_addr;

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uint32_t src1_size;

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uint16_t int_handle;

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union {

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uint16_t compr_flags;

[258] Fix | Delete

uint16_t decompr_flags;

[259] Fix | Delete

};

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uint64_t src2_addr;

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uint32_t max_dst_size;

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uint32_t src2_size;

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uint32_t filter_flags;

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uint32_t num_inputs;

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} __attribute__((packed));

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[267] Fix | Delete

struct dsa_raw_desc {

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uint64_t field[8];

[269] Fix | Delete

} __attribute__((packed));

[270] Fix | Delete

[271] Fix | Delete

/*

[272] Fix | Delete

* The status field will be modified by hardware, therefore it should be

[273] Fix | Delete

* __volatile__ and prevent the compiler from optimize the read.

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*/

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struct dsa_completion_record {

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__volatile__ uint8_t status;

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union {

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uint8_t result;

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uint8_t dif_status;

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};

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uint16_t rsvd;

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uint32_t bytes_completed;

[283] Fix | Delete

uint64_t fault_addr;

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union {

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/* common record */

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struct {

[287] Fix | Delete

uint32_t invalid_flags:24;

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uint32_t rsvd2:8;

[289] Fix | Delete

};

[290] Fix | Delete

[291] Fix | Delete

uint32_t delta_rec_size;

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uint64_t crc_val;

[293] Fix | Delete

[294] Fix | Delete

/* DIF check & strip */

[295] Fix | Delete

struct {

[296] Fix | Delete

uint32_t dif_chk_ref_tag;

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uint16_t dif_chk_app_tag_mask;

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uint16_t dif_chk_app_tag;

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};

[300] Fix | Delete

[301] Fix | Delete

/* DIF insert */

[302] Fix | Delete

struct {

[303] Fix | Delete

uint64_t dif_ins_res;

[304] Fix | Delete

uint32_t dif_ins_ref_tag;

[305] Fix | Delete

uint16_t dif_ins_app_tag_mask;

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uint16_t dif_ins_app_tag;

[307] Fix | Delete

};

[308] Fix | Delete

[309] Fix | Delete

/* DIF update */

[310] Fix | Delete

struct {

[311] Fix | Delete

uint32_t dif_upd_src_ref_tag;

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uint16_t dif_upd_src_app_tag_mask;

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uint16_t dif_upd_src_app_tag;

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uint32_t dif_upd_dest_ref_tag;

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uint16_t dif_upd_dest_app_tag_mask;

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uint16_t dif_upd_dest_app_tag;

[317] Fix | Delete

};

[318] Fix | Delete

[319] Fix | Delete

uint8_t op_specific[16];

[320] Fix | Delete

};

[321] Fix | Delete

} __attribute__((packed));

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[323] Fix | Delete

struct dsa_raw_completion_record {

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uint64_t field[4];

[325] Fix | Delete

} __attribute__((packed));

[326] Fix | Delete

[327] Fix | Delete

struct iax_completion_record {

[328] Fix | Delete

__volatile__ uint8_t status;

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uint8_t error_code;

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uint16_t rsvd;

[331] Fix | Delete

uint32_t bytes_completed;

[332] Fix | Delete

uint64_t fault_addr;

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uint32_t invalid_flags;

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uint32_t rsvd2;

[335] Fix | Delete

uint32_t output_size;

[336] Fix | Delete

uint8_t output_bits;

[337] Fix | Delete

uint8_t rsvd3;

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uint16_t xor_csum;

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uint32_t crc;

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uint32_t min;

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uint32_t max;

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uint32_t sum;

[343] Fix | Delete

uint64_t rsvd4[2];

[344] Fix | Delete

} __attribute__((packed));

[345] Fix | Delete

[346] Fix | Delete

struct iax_raw_completion_record {

[347] Fix | Delete

uint64_t field[8];

[348] Fix | Delete

} __attribute__((packed));

[349] Fix | Delete

[350] Fix | Delete

#endif

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