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* to the Linux Foundation.

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// $ATH_LICENSE_NULL$

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// @(#)queue.h 8.5 (Berkeley) 8/20/94

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* to the Linux Foundation.

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* Galois/Counter Mode (GCM) and GMAC with AES

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* AES-based functions

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* This program is free software; you can redistribute it and/or modify

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File: sha2.h

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* FILE: sha2.h

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* Redistribution and use in source and binary forms, with or without

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* are met:

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* Permission to use, copy, modify, and/or distribute this software for

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// -

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// $Id: //components/rel/wlanfw.cnss/1.0.1/cnss_proc/wlan/fw/target/src/wlan/proto/include/if_ethersubr.h#3 $

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File: wal_dfs.c

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* Permission to use, copy, modify, and/or distribute this software for

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File: ieee_crc32.c

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* polynomial is

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* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0

[1451] Fix | Delete

[1452] Fix | Delete

* Note that we take it "backwards" and put the highest-order term in

[1453] Fix | Delete

* the lowest-order bit. The X^32 term is "implied"; the LSB is the

[1454] Fix | Delete

* X^31 term, etc. The X^0 term (usually shown as "+1") results in

[1455] Fix | Delete

* the MSB being 1

[1456] Fix | Delete

[1457] Fix | Delete

* Note that the usual hardware shift register implementation, which

[1458] Fix | Delete

* is what we're using (we're merely optimizing it by doing eight-bit

[1459] Fix | Delete

* chunks at a time) shifts bits into the lowest-order term. In our

[1460] Fix | Delete

* implementation, that means shifting towards the right. Why do we

[1461] Fix | Delete

* do it this way? Because the calculated CRC must be transmitted in

[1462] Fix | Delete

* order from highest-order term to lowest-order term. UARTs transmit

[1463] Fix | Delete

* characters in order from LSB to MSB. By storing the CRC this way

[1464] Fix | Delete

* we hand it to the UART in the order low-byte to high-byte; the UART

[1465] Fix | Delete

* sends each low-bit to hight-bit; and the result is transmission bit

[1466] Fix | Delete

* by bit from highest- to lowest-order term without requiring any bit

[1467] Fix | Delete

* shuffling on our part. Reception works similarly

[1468] Fix | Delete

[1469] Fix | Delete

* The feedback terms table consists of 256, 32-bit entries. Notes

[1470] Fix | Delete

[1471] Fix | Delete

* The table can be generated at runtime if desired; code to do so

[1472] Fix | Delete

* is shown later. It might not be obvious, but the feedback

[1473] Fix | Delete

* terms simply represent the results of eight shift/xor opera

[1474] Fix | Delete

* tions for all combinations of data and CRC register values

[1475] Fix | Delete

[1476] Fix | Delete

* The values must be right-shifted by eight bits by the "updcrc

[1477] Fix | Delete

* logic; the shift must be unsigned (bring in zeroes). On some

[1478] Fix | Delete

* hardware you could probably optimize the shift in assembler by

[1479] Fix | Delete

* using byte-swap instructions

[1480] Fix | Delete

* polynomial $edb88320

[1481] Fix | Delete

[1482] Fix | Delete

[1483] Fix | Delete

* CRC32 code derived from work by Gary S. Brown.

[1484] Fix | Delete

[1485] Fix | Delete

================================================================================

[1486] Fix | Delete

File: aes.c

[1487] Fix | Delete

[1488] Fix | Delete

[1489] Fix | Delete

* For this file, which was received with alternative licensing options for

[1490] Fix | Delete

* distribution, Qualcomm Atheros, Inc. has selected the BSD license.

[1491] Fix | Delete

[1492] Fix | Delete

[1493] Fix | Delete

[1494] Fix | Delete

* AES (Rijndael) cipher

[1495] Fix | Delete

[1496] Fix | Delete

* Modifications to public domain implementation:

[1497] Fix | Delete

* - support only 128-bit keys

[1498] Fix | Delete

* - cleanup

[1499] Fix | Delete

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