# Chelsio T6 Factory Default configuration file.

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#

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# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.

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#

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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE

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# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE

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# TO ADAPTERS.

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# This file provides the default, power-on configuration for 2-port T6-based

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# adapters shipped from the factory. These defaults are designed to address

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# the needs of the vast majority of Terminator customers. The basic idea is to

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# have a default configuration which allows a customer to plug a Terminator

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# adapter in and have it work regardless of OS, driver or application except in

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# the most unusual and/or demanding customer applications.

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#

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# Many of the Terminator resources which are described by this configuration

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# are finite. This requires balancing the configuration/operation needs of

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# device drivers across OSes and a large number of customer application.

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#

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# Some of the more important resources to allocate and their constaints are:

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# 1. Virtual Interfaces: 256.

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# 2. Ingress Queues with Free Lists: 1024.

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# 3. Egress Queues: 128K.

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# 4. MSI-X Vectors: 1088.

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# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination

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# address matching on Ingress Packets.

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#

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# Some of the important OS/Driver resource needs are:

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# 6. Some OS Drivers will manage all resources through a single Physical

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# Function (currently PF4 but it could be any Physical Function).

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# 7. Some OS Drivers will manage different ports and functions (NIC,

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# storage, etc.) on different Physical Functions. For example, NIC

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# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.

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#

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# Some of the customer application needs which need to be accommodated:

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# 8. Some customers will want to support large CPU count systems with

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# good scaling. Thus, we'll need to accommodate a number of

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# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs

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# to be involved per port and per application function. For example,

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# in the case where all ports and application functions will be

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# managed via a single Unified PF and we want to accommodate scaling up

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# to 8 CPUs, we would want:

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#

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# 2 ports *

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# 3 application functions (NIC, FCoE, iSCSI) per port *

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# 16 Ingress Queue/MSI-X Vectors per application function

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#

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# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.

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# (Plus a few for Firmware Event Queues, etc.)

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#

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# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual

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# Machines to directly access T6 functionality via SR-IOV Virtual Functions

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# and "PCI Device Passthrough" -- this is especially true for the NIC

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# application functionality.

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#

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# Global configuration settings.

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#

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[global]

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rss_glb_config_mode = basicvirtual

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rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp

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# PL_TIMEOUT register

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pl_timeout_value = 200 # the timeout value in units of us

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# The following Scatter Gather Engine (SGE) settings assume a 4KB Host

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# Page Size and a 64B L1 Cache Line Size. It programs the

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# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.

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# If a Master PF Driver finds itself on a machine with different

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# parameters, then the Master PF Driver is responsible for initializing

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# these parameters to appropriate values.

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#

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# Notes:

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# 1. The Free List Buffer Sizes below are raw and the firmware will

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# round them up to the Ingress Padding Boundary.

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# 2. The SGE Timer Values below are expressed below in microseconds.

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# The firmware will convert these values to Core Clock Ticks when

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# it processes the configuration parameters.

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#

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reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL

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reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE

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reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD

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reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0

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reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1

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reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2

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reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3

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reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4

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reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5

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reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6

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reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7

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reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8

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sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs

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reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread

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# Set the SGE Doorbell Queue Timer "tick" to 50us and initialize

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# the Timer Table to a default set of values (which are multiples

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# of the Timer Tick). Note that the set of Tick Multipliers are

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# NOT sorted. The Host Drivers are expected to pick amongst them

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# for (Tick * Multiplier[i]) values which most closely match the Host

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# Drivers' needs. Also, most Host Drivers will be default start

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# start with (Tick * Multiplier[0]), so this gives us some flexibility

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# in terms of picking a Tick and a default Multiplier somewhere in

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# the middle of the achievable set of (Tick * Multiplier[i]) values.

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# Thus, the below select for 150us by this default.

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#

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sge_dbq_timertick = 50

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sge_dbq_timer = 3, 2, 1, 5, 7, 9, 12, 16

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# enable TP_OUT_CONFIG.IPIDSPLITMODE

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# Set TP_OUT_CONFIG.CCplAckMode to get srtt/rttvar

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reg[0x7d04] = 0x00012000/0x00012000

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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT

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#Tick granularities in kbps

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tsch_ticks = 100000, 10000, 1000, 10

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# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram

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# filter control: compact, fcoemask

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# server sram : srvrsram

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# filter tuples : fragmentation, mpshittype, macmatch, ethertype,

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# protocol, tos, vlan, vnic_id, port, fcoe

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# valid filterModes are described the Terminator 5 Data Book

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# vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation

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filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe

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# filter tuples enforced in LE active region (equal to or subset of filterMode)

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filterMask = protocol, fcoe

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# Percentage of dynamic memory (in either the EDRAM or external MEM)

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# to use for TP RX payload

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tp_pmrx = 30

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# TP RX payload page size

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tp_pmrx_pagesize = 64K

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# TP number of RX channels

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tp_nrxch = 0 # 0 (auto) = 1

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# Percentage of dynamic memory (in either the EDRAM or external MEM)

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# to use for TP TX payload

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tp_pmtx = 50

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# TP TX payload page size

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tp_pmtx_pagesize = 64K

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# TP number of TX channels

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tp_ntxch = 0 # 0 (auto) = equal number of ports

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# TP OFLD MTUs

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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600

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# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC

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reg[0x7d04] = 0x00010008/0x00010008

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# TP_GLOBAL_CONFIG

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reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable

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# TP_PC_CONFIG

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reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError

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# TP_PARA_REG0

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reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6

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# ULPRX iSCSI Page Sizes

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reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K

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# LE_DB_CONFIG

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reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled

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# LE IPv4 compression disabled

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# LE_DB_HASH_CONFIG

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reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,

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# ULP_TX_CONFIG

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reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err

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# Enable more error msg for ...

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# TPT error.

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# ULP_RX_MISC_FEATURE_ENABLE

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#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit

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# Enable offset decrement after ...

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# PI extraction and before DDP

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# ulp insert pi source info in DIF

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# iscsi_eff_offset_en

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#Enable iscsi completion moderation feature

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reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after

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# PI extraction and before DDP.

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# ulp insert pi source info in

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# DIF.

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# Enable iscsi hdr cmd mode.

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# iscsi force cmd mode.

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# Enable iscsi cmp mode.

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# MC configuration

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#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC

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# HMA configuration

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hma_size = 92 # Size (in MBs) of host memory expected

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hma_regions = stag,pbl,rq # What all regions to place in host memory

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#enable bottleneck-bw congestion control mode

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#ofld_flags = 4

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# Some "definitions" to make the rest of this a bit more readable. We support

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# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"

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# per function per port ...

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#

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# NMSIX = 1088 # available MSI-X Vectors

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# NVI = 256 # available Virtual Interfaces

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# NMPSTCAM = 336 # MPS TCAM entries

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#

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# NPORTS = 2 # ports

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# NCPUS = 16 # CPUs we want to support scalably

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# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)

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# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified

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# PF" which many OS Drivers will use to manage most or all functions.

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#

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# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can

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# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue

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# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue

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# will be specified as the "Ingress Queue Asynchronous Destination Index."

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# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less

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# than or equal to the number of Ingress Queues ...

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#

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# NVI_NIC = 4 # NIC access to NPORTS

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# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists

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# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues

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# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)

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# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)

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# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)

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#

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# NVI_OFLD = 0 # Offload uses NIC function to access ports

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# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists

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# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues

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# NEQ_OFLD = 16 # Offload Egress Queues (FL)

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# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)

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# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)

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#

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# NVI_RDMA = 0 # RDMA uses NIC function to access ports

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# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists

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# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues

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# NEQ_RDMA = 4 # RDMA Egress Queues (FL)

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# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)

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# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)

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#

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# NEQ_WD = 128 # Wire Direct TX Queues and FLs

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# NETHCTRL_WD = 64 # Wire Direct TX Queues

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# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists

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#

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# NVI_ISCSI = 4 # ISCSI access to NPORTS

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# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists

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# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues

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# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)

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# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)

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# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)

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#

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# NVI_FCOE = 4 # FCOE access to NPORTS

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# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists

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# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues

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# NEQ_FCOE = 66 # FCOE Egress Queues (FL)

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# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)

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# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)

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# Two extra Ingress Queues per function for Firmware Events and Forwarded

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# Interrupts, and two extra interrupts per function for Firmware Events (or a

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# Forwarded Interrupt Queue) and General Interrupts per function.

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#

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# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and

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# # Forwarded Interrupts

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# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and

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# # General Interrupts

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# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have

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# their interrupts forwarded to another set of Forwarded Interrupt Queues.

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#

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# NVI_HYPERV = 16 # VMs we want to support

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# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM

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# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues

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# NEQ_HYPERV = 32 # VIQs Free Lists

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# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)

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# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues

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# Adding all of the above Unified PF resource needs together: (NIC + OFLD +

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# RDMA + ISCSI + FCOE + EXTRA + HYPERV)

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#

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# NVI_UNIFIED = 28

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# NFLIQ_UNIFIED = 106

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# NETHCTRL_UNIFIED = 32

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# NEQ_UNIFIED = 124

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# NMPSTCAM_UNIFIED = 40

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#

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# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round

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# that up to 128 to make sure the Unified PF doesn't run out of resources.

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#

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# NMSIX_UNIFIED = 128

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#

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# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors

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# which is 34 but they're probably safe with 32.

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#

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# NMSIX_STORAGE = 32

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# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions

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# associated with it. Thus, the MSI-X Vector allocations we give to the

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# UnifiedPF aren't inherited by any Virtual Functions. As a result we can

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# provision many more Virtual Functions than we can if the UnifiedPF were

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# one of PF0-3.

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#

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# All of the below PCI-E parameters are actually stored in various *_init.txt

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# files. We include them below essentially as comments.

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#

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# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated

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# ports 0-3.

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#

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# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.

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#

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# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI

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# storage applications across all four possible ports.

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#

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# Additionally, since the UnifiedPF isn't one of the per-port Physical

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# Functions, we give the UnifiedPF and the PF0-3 Physical Functions

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# different PCI Device IDs which will allow Unified and Per-Port Drivers

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# to directly select the type of Physical Function to which they wish to be

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# attached.

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#

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# Note that the actual values used for the PCI-E Intelectual Property will be

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# 1 less than those below since that's the way it "counts" things. For

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# readability, we use the number we actually mean ...

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#

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# PF0_INT = 8 # NCPUS

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# PF1_INT = 8 # NCPUS

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# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT

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#

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# PF4_INT = 128 # NMSIX_UNIFIED

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# PF5_INT = 32 # NMSIX_STORAGE

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# PF6_INT = 32 # NMSIX_STORAGE

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# PF7_INT = 0 # Nothing Assigned

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# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT

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#

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# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT

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#

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# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)

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# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...

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#

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# NVF = 16

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# For those OSes which manage different ports on different PFs, we need

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# only enough resources to support a single port's NIC application functions

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# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue

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# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be

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# managed on the "storage PFs" (see below).

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#

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[function "0"]

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nvf = 16 # NVF on this function

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wx_caps = all # write/execute permissions for all commands

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r_caps = all # read permissions for all commands

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nvi = 1 # 1 port

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niqflint = 8 # NCPUS "Queue Sets"

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nethctrl = 8 # NCPUS "Queue Sets"

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neq = 16 # niqflint + nethctrl Egress Queues

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nexactf = 8 # number of exact MPSTCAM MAC filters

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cmask = all # access to all channels

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pmask = 0x1 # access to only one port

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[function "1"]

[370] Fix | Delete

nvf = 16 # NVF on this function

[371] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[372] Fix | Delete

r_caps = all # read permissions for all commands

[373] Fix | Delete

nvi = 1 # 1 port

[374] Fix | Delete

niqflint = 8 # NCPUS "Queue Sets"

[375] Fix | Delete

nethctrl = 8 # NCPUS "Queue Sets"

[376] Fix | Delete

neq = 16 # niqflint + nethctrl Egress Queues

[377] Fix | Delete

nexactf = 8 # number of exact MPSTCAM MAC filters

[378] Fix | Delete

cmask = all # access to all channels

[379] Fix | Delete

pmask = 0x2 # access to only one port

[380] Fix | Delete

[381] Fix | Delete

[function "2"]

[382] Fix | Delete

nvf = 16 # NVF on this function

[383] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[384] Fix | Delete

r_caps = all # read permissions for all commands

[385] Fix | Delete

nvi = 1 # 1 port

[386] Fix | Delete

niqflint = 8 # NCPUS "Queue Sets"

[387] Fix | Delete

nethctrl = 8 # NCPUS "Queue Sets"

[388] Fix | Delete

neq = 16 # niqflint + nethctrl Egress Queues

[389] Fix | Delete

nexactf = 8 # number of exact MPSTCAM MAC filters

[390] Fix | Delete

cmask = all # access to all channels

[391] Fix | Delete

pmask = 0x4 # access to only one port

[392] Fix | Delete

[393] Fix | Delete

[function "3"]

[394] Fix | Delete

nvf = 16 # NVF on this function

[395] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[396] Fix | Delete

r_caps = all # read permissions for all commands

[397] Fix | Delete

nvi = 1 # 1 port

[398] Fix | Delete

niqflint = 8 # NCPUS "Queue Sets"

[399] Fix | Delete

nethctrl = 8 # NCPUS "Queue Sets"

[400] Fix | Delete

neq = 16 # niqflint + nethctrl Egress Queues

[401] Fix | Delete

nexactf = 8 # number of exact MPSTCAM MAC filters

[402] Fix | Delete

cmask = all # access to all channels

[403] Fix | Delete

pmask = 0x8 # access to only one port

[404] Fix | Delete

[405] Fix | Delete

[406] Fix | Delete

# Some OS Drivers manage all application functions for all ports via PF4.

[407] Fix | Delete

# Thus we need to provide a large number of resources here. For Egress

[408] Fix | Delete

# Queues we need to account for both TX Queues as well as Free List Queues

[409] Fix | Delete

# (because the host is responsible for producing Free List Buffers for the

[410] Fix | Delete

# hardware to consume).

[411] Fix | Delete

#

[412] Fix | Delete

[function "4"]

[413] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[414] Fix | Delete

r_caps = all # read permissions for all commands

[415] Fix | Delete

nvi = 28 # NVI_UNIFIED

[416] Fix | Delete

niqflint = 218 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)

[417] Fix | Delete

nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside

[418] Fix | Delete

neq = 256 # NEQ_UNIFIED + NEQ_WD

[419] Fix | Delete

nqpcq = 12288

[420] Fix | Delete

nexactf = 40 # NMPSTCAM_UNIFIED

[421] Fix | Delete

nrawf = 2

[422] Fix | Delete

cmask = all # access to all channels

[423] Fix | Delete

pmask = all # access to all four ports ...

[424] Fix | Delete

nethofld = 1024 # number of user mode ethernet flow contexts

[425] Fix | Delete

ncrypto_lookaside = 16 # Number of lookaside flow contexts

[426] Fix | Delete

nclip = 320 # number of clip region entries

[427] Fix | Delete

nfilter = 496 # number of filter region entries

[428] Fix | Delete

nserver = 496 # number of server region entries

[429] Fix | Delete

nhash = 12288 # number of hash region entries

[430] Fix | Delete

nhpfilter = 64 # number of high priority filter region entries

[431] Fix | Delete

protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, nic_hashfilter, nic_ktls_ofld

[432] Fix | Delete

tp_l2t = 3072

[433] Fix | Delete

tp_ddp = 2

[434] Fix | Delete

tp_ddp_iscsi = 2

[435] Fix | Delete

tp_tls_key = 2

[436] Fix | Delete

tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes

[437] Fix | Delete

tp_stag = 2

[438] Fix | Delete

tp_pbl = 7

[439] Fix | Delete

tp_rq = 7

[440] Fix | Delete

tp_srq = 128

[441] Fix | Delete

[442] Fix | Delete

# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may

[443] Fix | Delete

# need to have Virtual Interfaces on each of the four ports with up to NCPUS

[444] Fix | Delete

# "Queue Sets" each.

[445] Fix | Delete

#

[446] Fix | Delete

[function "5"]

[447] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[448] Fix | Delete

r_caps = all # read permissions for all commands

[449] Fix | Delete

nvi = 4 # NPORTS

[450] Fix | Delete

niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA

[451] Fix | Delete

nethctrl = 32 # NPORTS*NCPUS

[452] Fix | Delete

neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)

[453] Fix | Delete

nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.

[454] Fix | Delete

cmask = all # access to all channels

[455] Fix | Delete

pmask = all # access to all four ports ...

[456] Fix | Delete

nserver = 16

[457] Fix | Delete

nhash = 2048

[458] Fix | Delete

tp_l2t = 1020

[459] Fix | Delete

nclip = 64

[460] Fix | Delete

protocol = iscsi_initiator_fofld

[461] Fix | Delete

tp_ddp_iscsi = 2

[462] Fix | Delete

iscsi_ntask = 2048

[463] Fix | Delete

iscsi_nsess = 2048

[464] Fix | Delete

iscsi_nconn_per_session = 1

[465] Fix | Delete

iscsi_ninitiator_instance = 64

[466] Fix | Delete

[467] Fix | Delete

[468] Fix | Delete

[function "6"]

[469] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[470] Fix | Delete

r_caps = all # read permissions for all commands

[471] Fix | Delete

nvi = 4 # NPORTS

[472] Fix | Delete

niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA

[473] Fix | Delete

nethctrl = 32 # NPORTS*NCPUS

[474] Fix | Delete

neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)

[475] Fix | Delete

nexactf = 32 # NPORTS + adding 28 exact entries for FCoE

[476] Fix | Delete

# which is OK since < MIN(SUM PF0..3, PF4)

[477] Fix | Delete

# and we never load PF0..3 and PF4 concurrently

[478] Fix | Delete

cmask = all # access to all channels

[479] Fix | Delete

pmask = all # access to all four ports ...

[480] Fix | Delete

nhash = 2048

[481] Fix | Delete

tp_l2t = 4

[482] Fix | Delete

protocol = fcoe_initiator

[483] Fix | Delete

tp_ddp = 1

[484] Fix | Delete

fcoe_nfcf = 16

[485] Fix | Delete

fcoe_nvnp = 32

[486] Fix | Delete

fcoe_nssn = 1024

[487] Fix | Delete

[488] Fix | Delete

[489] Fix | Delete

# The following function, 1023, is not an actual PCIE function but is used to

[490] Fix | Delete

# configure and reserve firmware internal resources that come from the global

[491] Fix | Delete

# resource pool.

[492] Fix | Delete

#

[493] Fix | Delete

[function "1023"]

[494] Fix | Delete

wx_caps = all # write/execute permissions for all commands

[495] Fix | Delete

r_caps = all # read permissions for all commands

[496] Fix | Delete

nvi = 4 # NVI_UNIFIED

[497] Fix | Delete

cmask = all # access to all channels

[498] Fix | Delete

pmask = all # access to all four ports ...

[499] Fix | Delete